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en:xu4_hardware [2017/06/16 10:57] luke.go [Specifications] |
en:xu4_hardware [2017/07/13 14:29] (current) john1117 [Expansion Connectors] |
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| |HDD/SSD SATA interface (Optional)|SuperSpeed USB (USB 3.0) to Serial ATA3 adapter for 2.5"/3.5" HDD and SSD storage| | |HDD/SSD SATA interface (Optional)|SuperSpeed USB (USB 3.0) to Serial ATA3 adapter for 2.5"/3.5" HDD and SSD storage| | ||
| |Power (included)|5V 4A Power| | |Power (included)|5V 4A Power| | ||
| - | |Case(Option)|Mechanical case & cooler (98 x 74 x 29 mm approx. )| | + | |Case(Option)|Mechanical case & cooler (90 x 59 x 28 mm approx. )| |
| |PCB Size|83 x 58 x 20 mm approx.| | |PCB Size|83 x 58 x 20 mm approx.| | ||
| Line 39: | Line 39: | ||
| The XU3/XU4 povides one 30-pin dual row expansion header "**CON10**". \\ | The XU3/XU4 povides one 30-pin dual row expansion header "**CON10**". \\ | ||
| The location and pinout of these connectors is illustrated blew. All signals on expansion headers are 1.8V except PWRON signal. \\ | The location and pinout of these connectors is illustrated blew. All signals on expansion headers are 1.8V except PWRON signal. \\ | ||
| + | |||
| + | {{:en:xu4:xu4.png?600|}} | ||
| + | |||
| ---- | ---- | ||
| **CON10 - 2x15 pins** | **CON10 - 2x15 pins** | ||
| - | ^ Pin Number ^ Net Name ^ GPIO & Export No ^ Default Pin State ^ Pin Number ^ Net Name ^ GPIO & Export No ^ Default Pin State ^ | + | ^ Pin Number ^ Net Name ^ GPIO & Export No ^ Default Pin State ^ Pin Number ^ Net Name ^ GPIO & Export No ^ Default Pin State ^ |
| - | | 1 | 5V0 | | | 2 | GND | | | | + | | 1 | 5V0 | | | 2 | GND | | | |
| - | | 3 | ADC_0.AIN0 | XADC0AIN_0 | I | 4 | UART_0.CTSN | GPA0.2 (#173) | I(PUDN) | | + | | 3 | ADC_0.AIN0 | XADC0AIN_0 | I | 4 | UART_0.CTSN | GPA0.2 (#173) | I(PUDN) | |
| - | | 5 | UART_0.RTSN | GPA0.3 (#174) | I(PUDN) | 6 | UART_0.RXD | GPA0.0 (#171) | I(PUDN) | | + | | 5 | UART_0.RTSN | GPA0.3 (#174) | I(PUDN) | 6 | UART_0.RXD | GPA0.0 (#171) | I(PUDN) | |
| - | | 7 | SPI_1.MOISI | GPA2.7 (#192) | I(PUDN) | 8 | UART_0.TXD | GPA0.1 (#172) | I(PUDN) | | + | | 7 | SPI_1.MOISI | GPA2.7 (#192) | I(PUDN) | 8 | UART_0.TXD | GPA0.1 (#172) | I(PUDN) | |
| - | | 9 | SPI_1.MISO | GPA2.6 (#191) | I(PUDN) | 10 | SPI_1.CLK | GPA2.4 (#189) | I(PUDN) | | + | | 9 | SPI_1.MISO | GPA2.6 (#191) | I(PUDN) | 10 | SPI_1.CLK | GPA2.4 (#189) | I(PUDN) | |
| - | | 11 | SPI_1.CSN | GPA2.5 (#190) | I(PUDN) | 12 | PWRON | | I | | + | | 11 | SPI_1.CSN | GPA2.5 (#190) | I(PUDN) | 12 | PWRON | Input Range (1.8V ~ 5V)| I | |
| - | | 13 | XE.INT13 | GPX1.5 (#21) | I(PUDN) | 14 | I2C_1.SCL | GPB3.3 (#210) | I(PUDN) | | + | | 13 | XE.INT13 | GPX1.5 (#21) | I(PUDN) | 14 | I2C_1.SCL | GPB3.3 (#210) | I(PUDN) | |
| - | | 15 | XE.INT10 | GPX1.2 (#18) | I(PUDN) | 16 | I2C_1.SDA | GPB3.2 (#209) | I(PUDN) | | + | | 15 | XE.INT10 | GPX1.2 (#18) | I(PUDN) | 16 | I2C_1.SDA | GPB3.2 (#209) | I(PUDN) | |
| - | | 17 | XE.INT14 | GPX1.6 (#22) | I(PUDN) | 18 | XE.INT11 | GPX1.3 (#19) | I(PUDN) | | + | | 17 | XE.INT14 | GPX1.6 (#22) | I(PUDN) | 18 | XE.INT11 | GPX1.3 (#19) | I(PUDN) | |
| - | | 19 | XE.INT22 | GPX2.6 (#30) | I(PUDN) | 20 | XE.INT20 | GPX2.4 (#28) | I(PUDN) | | + | | 19 | XE.INT22 | GPX2.6 (#30) | I(PUDN) | 20 | XE.INT20 | GPX2.4 (#28) | I(PUDN) | |
| - | | 21 | XE.INT21 | GPX2.5 (#29) | I(PUDN) | 22 | XE.INT23 | GPX2.7 (#31) | I(PUDN) | | + | | 21 | XE.INT21 | GPX2.5 (#29) | I(PUDN) | 22 | XE.INT23 | GPX2.7 (#31) | I(PUDN) | |
| - | | 23 | ADC_0.AIN3 | XADC0AIN_3 | I | 24 | XE.INT17 | GPX2.1 (#25) | I(PUDN) | | + | | 23 | ADC_0.AIN3 | XADC0AIN_3 | I | 24 | XE.INT17 | GPX2.1 (#25) | I(PUDN) | |
| - | | 25 | XE.INT15 | GPX1.7 (Soft I2C SCL) (#23) | I(PUDN) | 26 | XE.INT16 | GPX2.0 (#24) | I(PUDN) | | + | | 25 | XE.INT15 | GPX1.7 (#23) | I(PUDN) | 26 | XE.INT16 | GPX2.0 (#24) | I(PUDN) | |
| - | | 27 | XE.INT25 | GPX3.1 (Soft I2C SDA) (#33) | I(PUDN) | 28 | GND | | | | + | | 27 | XE.INT25 | GPX3.1 (#33) | I(PUDN) | 28 | GND | | | |
| - | | 29 | VDD_IO(1.8V) | | | 30 | GND | | | | + | | 29 | VDD_IO(1.8V) | | | 30 | GND | | | |
| ---- | ---- | ||
| + | |||
| + | {{:en:xu4:xu4_con10.png?817|}} | ||
| **CON11 - 2x6 pins** | **CON11 - 2x6 pins** | ||
| Line 71: | Line 76: | ||
| | 11 | I2S_0.LRCK | GPZ.2 (#227) | I(PUDN) | 12 | I2S_0.SDI | GPZ.3 (#228) | I(PUDN) | | | 11 | I2S_0.LRCK | GPZ.2 (#227) | I(PUDN) | 12 | I2S_0.SDI | GPZ.3 (#228) | I(PUDN) | | ||
| + | {{:en:xu4:xu4_con11_2.png?600|}} | ||
| **[[http://dn.odroid.com/5422/ODROID-XU3/Schematics/XU4_HIGHTOPSILK.png|PCB Layout for pin map]]** | **[[http://dn.odroid.com/5422/ODROID-XU3/Schematics/XU4_HIGHTOPSILK.png|PCB Layout for pin map]]** | ||
